Semiconductor memory systems are comprised of two basic elements: memory storage areas and memory control areas. DRAM, for example, includes a memory cell array, which stores information, and peripheral circuitry, which controls the operation of the memory cell array.
DRAM arrays are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. A DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a storage capacitor and an access field effect transistor.
FIG. 1 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 10. For each cell, one side of the storage capacitor 14 is connected to a reference voltage, which is typically one half of the internal operating voltage (the voltage corresponding to a logical xe2x80x9c1xe2x80x9d signal) of the circuit. The other side of the storage capacitor 14 is connected to the drain of the access field effect transistor 12. The gate of the access field effect transistor 12 is connected to a signal referred to as the wordline 11. The source of the field effect transistor 12 is connected to a signal referred to as the bit line 15. With the circuit connected in this manner, it is apparent that the wordline controls access to the storage capacitor 14 by allowing or preventing the signal (a logic xe2x80x9c0xe2x80x9d or a logic xe2x80x9c1xe2x80x9d) on the bit line 15 to be written to or read from the storage capacitor 14.
The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the wordline, and the reference voltage. DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and increase memory cell density to allow more memory to be squeezed onto a single memory chip. However, it is necessary to maintain a sufficiently high storage capacitance to maintain a charge at the refresh rates currently in use even as cell size continues to shrink. This requirement has led DRAM manufacturers to turn to three dimensional capacitor designs, including trench and stacked capacitors. Stacked capacitors are capacitors which are stacked, or placed, over the access transistor in a semiconductor device. In contrast, trench capacitors are formed in the wafer substrate beneath the transistor. For reasons including ease of fabrication and increased capacitance, most manufacturers of DRAMs larger than 4 Megabits use stacked capacitors. Therefore, the invention will be discussed in connection with stacked capacitors but should not be understood to be limited thereto. For example, use of the invention in connection with trench or planar capacitors is also possible.
One widely used type of stacked capacitor is known as a container capacitor. Known container capacitors are in the shape of an upstanding tube (cylinder) having an oval or circular cross section. The wall of the tube consists of two plates of conductive material such as doped polycrystalline silicon (referred to herein as polysilicon or poly) separated by a dielectric. The bottom end of the tube is closed, with the outer wall in contact with either the drain of the access transistor or a plug which itself is in contact with the drain. The other end of the tube is open (the tube is filled with an insulative material later in the fabrication process). The sidewall and closed end of the tube form a container; hence the name xe2x80x9ccontainer capacitor.xe2x80x9d Although the invention will be further discussed in connection with stacked container capacitors, the invention should not be understood to be limited thereto.
The peripheral circuitry communicates with and controls the storage operations of the memory cell array through interconnection layers (or interconnects) usually formed from aluminum or other metal. FIG. 2 is a block diagram of a DRAM including peripherial circuitry. Referring to FIG. 2, DRAM 50 comprises: a memory cell array 51 for storing data signals of memory information; a row and column address buffer 52 for receiving external address signals for selecting a memory cell; a row decoder 53 and a column decoder 54 for designating the memory cell by decoding the address signals; a sense refresh amplifier 55 for amplifying and reading a signal stored in the designated memory cell; a data-in buffer 56 and a data-out buffer 57 for inputting/outputting data; and a clock generator 58 for generating a clock signal.
Frequently, as in the case of microprocessors, microcontrollers, and other application specific integrated circuitry (ASICs), it is desired to incorporate ROM together with or in addition to RAM on a single semiconductor wafer. This typically requires the formation of separate additional peripheral circuitry and interconnects for the ROM. The ROM cells and additional circuitry require additional semiconductor wafer space and fabrication process steps which increase the overall costs of device fabrication.
The goal of increasing or, at least, maintaining memory capacity as cell size shrinks must be attained without resorting to processes that increase the number of masking, deposition, etch and other steps in the production process. This has a great impact on manufacturing costs, particularly the costs of photolithographic steps. High capital costs are associated with photolithographic equipment and more complex photo processing, in terms of more photo process steps per level, more equipment, and the use of expensive ultra clean room floor space. Defect density is inevitably increased with each additional photomasking layer and compromises yield and reliability. All photo layers also require a subsequent step, either implant or etch. These additional steps further add to manufacturing costs.
What is needed is a ROM-embedded-DRAM, for ASICs and the like, which can be fabricated with a minimum of process steps.
The present invention provides ROM-embedded-DRAM and a fabrication method in which a ROM is embedded within an array of DRAM cells. The ROM cells may be fabricated by changing a single mask in the DRAM fabrication process to selectively short circuit the DRAM capacitor lower electrode to its own wordline to create a read-only xe2x80x9c1xe2x80x9d or to the wordline of an adjacent cell to create a read only xe2x80x9c0xe2x80x9d. The selective shorting may be achieved by shifting one mask opening, preferably the mask used for etching the opening for the capacitor storage node or plug. Shifting the mask either toward the desired read-only bit""s wordline or the read-only bit""s adjacent wordline programs the ROM bits, while the same mask openings on the DRAM cells are not changed. The ROM cells can use the same peripheral circuitry and interconnects as the DRAM cells on the same chip.